This application claims priority from Korean Patent Application No. 2002-12563, filed on Mar. 8, 2002, and Korean Patent Application No. 2002-65610, filed on Oct. 25, 2002, the contents of which are incorporated herein by this reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a ferroelectric memory device including a ferroelectric capacitor and a method for manufacturing the same.
2. Description of the Related Art
Ferroelectric memory devices using a ferroelectric layer have recently been recognized as ideal memory devices for next generation electronic devices. Ferroelectric memory devices work by controlling a direction of polarization based on a direction of an applied electric field. A digital xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is stored in the ferroelectric memory device according to a direction of remnant polarization remaining after the electric field is removed. These ferroelectric memory devices are characterized by high endurance, high speed (e.g., tens of nanoseconds), low driving voltage (e.g., less than 5V), and low power dissipation. However, in addition to these characteristics, the ferroelectric memory device must also be highly integrated to be useful as a memory product.
To achieve high integration of a ferroelectric memory device, the ferroelectric capacitor embodied in the 1 transistor/1 ferroelectric capacitor (1T/1C) cell structure of the memory device should be miniaturized and multiple wiring processes should be developed. Hot temperature retention as well as powerful writing and reading abilities (compared to Dynamic Random Access Memory (DRAM) and Static RAM (SRAM) devices) should also be provided. Miniaturization of the ferroelectric capacitor, in particular, is an important and complicated technology in improving the integration of the ferroelectric memory device. This is because changes in ferroelectricity due to reductions in size of ferroelectric capacitor regions should be studied and verified. Further, subsequent processes on smaller capacitors become more difficult. Via holes in each cell should be connected to plate lines to provide the desired characteristics of the ferroelectric memory device. The conventional method for manufacturing via holes in each cell is not usable in a capacitor region with a design rule of less than 0.25 xcexcm.
Accordingly, there is a need for improved technology for forming via holes to connect plate lines to smaller capacitors. This technology should not damage the capacitor. Damage can occur due to etching chemicals (gas or solution) that impair the capacitor by degrading the remnant polarization or its distribution. Because the operation of a ferroelectric memory device relies on recognizing the difference between the remnant polarization of a reference cell capacitor and a memory cell capacitor, if the distribution of remnant polarization in the capacitors is irregular, it reduces the sensing margin of the ferroelectric memory device.
The present invention provides a more integrated ferroelectric memory device by improving the connection between plate lines and a ferroelectric capacitor.
The present invention also provides methods for manufacturing a ferroelectric memory device including methods for forming via holes in a highly integrated ferroelectric memory device, without degrading the characteristic of a capacitor.
According to one embodiment of the present invention, a ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors.
According to another embodiment of the present invention, a ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed between the ferroelectric capacitors and extending to substantially the same height as the ferroelectric capacitors, leaving a top surface of the capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving a top surface of the interlayer insulation layer exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to at least two adjacent ferroelectric capacitors.